1. Field of the Invention
This invention is related to transmitting data across clock domain boundaries and particularly to using FIFO buffers to transmit data across clock domain boundaries.
2. Description of the Related Art
Electronic systems often have two or more different clock domains, corresponding to different clock signals used in the system. The clock signals that form different clock domains may have different sources, and thus a phase relationship between the clock signals may not be known. The clock signals may have different frequencies. In some cases, the clock signals may have both different sources and different frequencies. Different clock domains may exist on a single integrated circuit, between integrated circuits in a system, or both.
Generally, transmitting data across clock domain boundaries requires some sort of synchronization to ensure that data is safely and accurately captured in the receiving clock domain. FIFO buffers are frequently used to transfer data between clock domains. The transmitting clock domain writes data into the buffer using a write pointer. Subsequently, after the data is known to be stable in the FIFO buffer, the receiving clock domain reads data from the buffer. To prevent overrun when the FIFO buffer is full, and to prevent underrun with the FIFO buffer is empty, FIFO control logic generates empty and full signals. The full signal is generated in the transmitting clock domain, and the empty signal is generated in the receiving clock domain. Typically, the full and empty signals are generated by comparing the read and write pointers. However, to compare the pointers, they must be transmitted between the clock domains.
Typically, the pointers are transmitted between the clock domains by dual-rank synchronizing the pointers (also referred to herein as double synchronizing the pointers). A pair of clocked storage devices are coupled in series, in the clock domain that receives a pointer for comparison. An input to the series connection receives the pointer from the other clock domain. After passing through the series connection, the pointer is considered stable in the clock domain and can be compared.
Double synchronizing is used to avoid metastability problems that may occur if setup/hold times are violated by a transition in the value of the pointer that is generated in the other clock domain. When such violations occur, the value captured by the clocked storage device may oscillate or an unpredictable value may be captured. Unfortunately, double synchronizing also introduces a two clock cycle latency in the clock domain to which the synchronization is performed. This latency complicates the interface to the FIFO buffer and/or complicates the FIFO design for generating the full/empty signals. Furthermore performance may be lost (e.g. the deassertion of the empty signal is delayed from the writing of new data, and thus the reading of the new data is also delayed).